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data sheet 28210.2 unipolar stepper-motor translator/pwm driver combining low-power cmos logic with high-current, high-voltage power fet outputs, the sla7050m translator/driver provides complete control and drive for a two-phase unipolar stepper motor with internal fixed off time, pulse-width modulation (pwm) control of the output current in a power multi-chip module (pmcm?). the cmos logic section provides the sequencing logic, direction, full/half-step control, synchronous/asynchronous pwm operation, and a ?sleep? function. the minimum clock input is an ideal fit for applications where a complex p is unavailable or overburdened. ttl or lsttl may require the use of appropriate pull-up resistors to ensure a proper input-logic high. for pwm current control, the maximum output current is determined by the user?s selection of a reference voltage and sensing resistor. the nmos outputs are capable of sinking up to 1 a and withstanding 46 v in the off state. ground-clamp and flyback diodes provide protection against inductive transients. special power-up sequencing is not required. full-step (2 phase) and half-step operation are externally selectable. two-phase drive energizes two adjacent phases in each detent position (ab-bc-cd-da). this sequence mode offers an improved torque- speed product, greater detent torque, and is less susceptable to motor resonance. half-step excitation alternates between the one-phase and two-phase modes (a-ab-b-bc-c-cd d-da), providing an eight-step sequence. the sla7050m is supplied in an 18-pin single in-line power-tab package with leads formed for vertical mounting (suffix lf871) or horizontal mounting (suffix lf872). the tab is at ground potential and needs no insulation. for high-current or high-frequency applications, external heat sinking may be required. this device is rated for continu- ous operation between -20c and +85c. f eatures ? 1 a output rating ? internal sequencer for full or half-step operation ? pwm constant-current motor drive ? cost-effective, multi-chip solution ? 100 v, avalanche-rated nmos ? low r ds(on) nmos outputs (700 m ? typical) ? advanced, improved body diodes ? half-step and full-step unipolar drive ? inputs compatible with 3.3 v or 5 v control signals ? sleep mode ? internal clamp diodes always order by complete part number, e.g., SLA7050MLF871 . a bsolute m aximum r atings driver supply voltage, v bb ................ 46 v load supply voltage, v m .................. 46 v output current, i o .......................... 1.0 a * logic supply voltage, v dd ............... 7.0 v logic input voltage range, v i ........................... -0.3 v to v dd + 0.3 v sense voltage, v s ........................ 2.0 v? reference input voltage range, v ref ................................... -0.3 v to v dd + 0.3 v package power dissipation, p d ........................................ see graph junction temperature, t j ............. +150c operating temperature range, t a ................................. -20c to +85c storage temperature range, t s ............................... -30c to +150c * output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or junction temperature. ? internal filtering provides protection against transients during the first 1 s of the current-sense pulse. sla7050m preliminary information (subject to change without notice) february 19, 2003
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 sla7050m unipolar stepper-motor translator/pwm driver 2 functional block diagram copyright ? 2003 allegro microsystems, inc. recommended operating conditions load supply voltage, v bb .................................. 10 to 44 v logic supply voltage, v dd ............................ 3.0 v to 5.5 v reference input voltage, v ref ...................... 0.1 v to 1.0 v tab temperature (no heat sink), t t ...................... <100c
sla7050m unipolar stepper-motor translator/pwm driver www.allegromicro.com 3 electrical characteristics: unless otherwise noted at t a = +25c, v bb = 24 v, v dd = 5.0 v. limits characteristic symbol test conditions min. typ. max. units output drivers driver supply volt. range v bb operating 10 ? 44 v drain-source breakdown v (br)ds v bb = 44 v, i d = 1 ma 100 ? ? v output on resistance r ds(on) i o = 1.0 a ? 700 850 m ? body diode forward volt. v f i f = 1.0 a ? 0.9 1.2 v driver supply current i bb ?? 15 ma v ref > 2.0 v (sleep mode) ? ? 100 a control logic logic supply volt. range v dd operating 3.0 5.0 5.5 v logic input voltage v ih 0.75v dd ?? v v il ? ? 0.25v dd v logic input current i ih ? 1.0 ? a i il ? 1.0 ? a max. clock frequency f clk 100* ? ? khz pwm off time t off ?12 ? s pwm min. on time t on(min) ? 5.0 ? s ref. input voltage range v ref operating 0.1 ? 1.0 v sleep mode 2.0 ? ? v ref. input current i ref ? 10 ? a sense voltage v s trip point ? v ref ?v propagation delay time t plh clock rising edge to output on ? 2.5 ? s t phl clock rising edge to output off ? 2.0 ? s logic supply current i dd ? ? 3.0 ma typical values are given for circuit design information only. *operation at a clock frequency greater than the specified minimum value is possible but not warranted.
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 sla7050m unipolar stepper-motor translator/pwm driver 4 timing chart logic input timing
sla7050m unipolar stepper-motor translator/pwm driver www.allegromicro.com 5 functional description device operation. the sla7050m is a complete stepper-motor driver with built-in translator for easy operation with minimal control lines. it is designed to operate unipolar stepper motors in full-step or half-step modes. the current in each pair of outputs, all n-channel mosfets, is regulated with internal fixed off-time pulse- width modulated (pwm) control circuitry. when a step command signal occurs on the clock input the translator automatically sequences to the next step. clock (step) input. a low-to-high transition on the clock input sequences the translator and advances the motor one increment. the hold state is done by stopping the clock input regardless of the input level full/half-step select. this logic-level input sets the translator step mode. a logic high is two-phase, full step; a logic low is half step. changes to this input do not take effect until the rising edge of the clock input. cw/ccw (direction) input. this logic-level input sets the translator step direction. changes to this input do not take effect until the rising edge of the clock input. internal pwm current control. each pair of outputs is controlled by a fixed off-time pwm current-control circuit that limits the load current to a desired value (i trip ). initially, an output is enabled and current flows through the motor winding and r s . when the voltage across the current-sense resistor equals the reference voltage, the current-sense comparator resets the pwm latch, which turns off the driver for the fixed off time during which the load inductance causes the current to recirculate for the off time period. the driver is then re-enabled and the cycle repeats. synchronous operation mode. this function pre- vents occasional motor noise during a ?hold? state, which normally results from asynchronous pwm operation of both motor phases. a logic high at the sync input is synchronous operation; a logic low is asynchronous operation. the use of synchronous operation during normal stepping is not recommended because it produces less motor torque and can cause motor vibration due to stair-case current. sleep mode. applying a voltage greater than 2 v to the ref pin disables the outputs and puts the motor in a free state (coast). this function is used to minimize power consumption when not in use. it disables much of the internal circuitry including the output mosfets and regulator. when coming out of sleep mode, wait 100 s before issuing a step command to allow the internal circuitry to stabilize.
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 sla7050m unipolar stepper-motor translator/pwm driver 6 applications information layout. the printed wirting board should use a heavy ground plane. for optimum electrical and thermal performance, the driver should be soldered directly into the board. the driver supply terminal, vbb, should be decoupled with an electrolytic capacitor placed as close to the device as possible. to avoid problems due to capacitive coupling of the high dv/dt switching transients, route the high-level, output traces away from the sensitive, low-level logic traces. always drive the logic inputs with a low source impedance to increase noise immunity. grounding. a star ground system located close to the driver is recommended. the logic supply return and the driver supply return should be connected together at only a single point ? the star ground. logic supply voltage, v dd . transients at this terminal should be held to less than 0.5 v to avoid malfunctioning operation. both v bb and v dd may be turned on or off separately. logic inputs. unused logic inputs (cw/ccw, full/ half, or sync) must be connected to either ground or the logic supply voltage. current sensing. to minimize inaccuracies caused by ground-trace ir drops in sensing the output current level, the current-sense resistor, r s , should have an independent ground return to the star ground of the device. this path should be as short as possible. for low-value sense resistors, the ir drops in the printed wiring board sense resistor?s traces can be significant and should be taken into account. the use of sockets should be avoided as they can introduce variation in r s due to their contact resistance. pwm current control. the maximum value of current limiting (i trip ) is set by the selection of r s and the voltage at the ref input with a transconductance function ap- proximated by: i trip = v ref /r s the required v ref should not be less than 0.1 v. if it is, r s should be increased for a proportionate increase in v ref . typical application sla7050m
sla7050m unipolar stepper-motor translator/pwm driver www.allegromicro.com 7 applications information (cont?d) continuous discontinuous mode mode normalized fet on resistance sync. signal generator reference voltage. in the typical application shown, resistors r 1 and r 2 set the reference voltage as: v ref = (v dd x r 2 )/(r 1 + r 2 ) the trimming of r 2 allows for the resistor tolerances and ref input current. the sum of r 1 +r 2 should be less than 50 k ? to minimize the effect of i ref . minimum output current. the sla7050m uses fixed off-time pwm current control. due to internal logic and switching delays, the actual load current peak will be slightly higher than the calculated i trip value (especially for low-inductance loads). these delays, plus the mini- mum recommended v ref , limit the minimum value the current-control circuitry can regulate. an application with this device should maintain continuous pwm control in order to obtain optimum torque out of the motor. the boundary of the load current (i o(min) ) between continuous and discontinuous operation is: i o(min) = [(v m + v sd )/r m ] x [(1/e t off /[r m x l m ] ) - 1] where v m = load supply voltage v f = body diode forward voltage r m = motor winding resistance t off = pwm off time l m = motor winding inductance to produce zero current in a motor, the ref input should be pulled above 2 v, turning off all drivers. synchronous operation mode. if an external signal is not available to control the synchronous operation mode, a simple circuit can keep the sync input low while the clock input is active; the sync input will go high (synchronous operation) when the clock input stays low (?hold?). the rc time constant determines the sync trransition timing. temperature effects on fet outputs. analyzing safe, reliable operation includes a concern for the relation- ship of nmos on resistance to junction temperature. device package power calculations must include the increase in on resistance (producing higher on voltages) caused by increased operating junction temperatures. the figure provides a normalized on-resistance curve, and all thermal calculations should consider increases from the io=0.5 a io=0.7 a io=1.0 a 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -50 -25 0 25 50 75 100 125 150 junction temperature in c vds(on) (v)
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 sla7050m unipolar stepper-motor translator/pwm driver 8 applications information (cont?d) allowable avalanche energy waveforms during avalanche breakdown given +25c limits, which may be caused by internal heating during normal operation. these power mosfet outputs feature an excellent combination of fast switching, ruggedized device design, low on resistance, and cost effectiveness. avalanche energy capability. there is a surge voltage expected when the output mosfet turns off, and this voltage may exceed the mosfet breakdown voltage (v (br)ds ). however, the mosfets are avalanche type and as long as the energy (e (av) ), which is imposed on the mosfet by the surge voltage, is less than the maximum allowable value, it is considered to be within its safe operating area. note that the maximum allowable ava- lanche energy is reduced as a function of temperature. in application, the avalanche energy (e (av) ) dissipated by the mosfet is approximated as e (av) = v ds(av) x 1/2 x i d x t output circuit for avalanche energy calculations
sla7050m unipolar stepper-motor translator/pwm driver www.allegromicro.com 9 terminal list terminal pin name terminal description 1 outa driver output for phase a 2 nu not usable 3 outa\ driver output for phase a\ 4 gatea phase a mosfet gate 5 vdd logic power supply, v dd 6 sensea phase a current sense 7 clock step clock input 8 sync synchronous pwm control input 9 ref current set & ?sleep? control 10 gnd supply negative return 11 cw/ccw forward/reverse logic control input 12 full/half full step/half step logic control input 13 senseb phase b current sense 14 vbb driver power supply, v bb 15 gateb phase b mosfet gate 16 outb\ driver output for phase b\ 17 nu not usable 18 outb driver output for phase b the products described herein are manufactured in japan by sanken electric co., ltd. for sale by allegro microsystems, inc. sanken and allegro reserve the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. therefore, the user is cautioned to verify that the information in this publication is current before placing any order. when using the products described herein, the applicability and suitability of such products for the intended purpose shall be reviewed at the users responsibility. although sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. users of sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to society due to device failure or malfunction. sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). their use in any application requiring radiation hardness assurance (e.g., aerospace equipment) is not supported. when considering the use of sanken products in applications where higher reliability is required (transportation equipment and its control systems or equipment, fire- or burglar-alarm systems, various safety devices, etc.), contact a sanken sales representative to discuss and obtain written confirmation of your specifications. the use of sanken products without the written consent of sanken in applications where extremely high reliability is required (aerospace equipment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited. the information included herein is believed to be accurate and reliable. application and operation examples described in this publication are given for reference only and sanken and allegro assume no responsibility for any infringement of industrial property rights, intellectual property rights, or any other rights of sanken or allegro or any third party that may result from its use.
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 sla7050m unipolar stepper-motor translator/pwm driver 10 notes: 1. exact body and lead configuration at vendor?s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. the shaded area is exposed heat spreader. 3. recommended mounting hardware torque: 0.490 - 0.822 nm. 4. recommended use of metal-oxide-filled, alkyl-degenerated oil-base silicone grease: dow corning sc102, toshiba yg6260, shin-etsu g746, or equivalent. SLA7050MLF871 dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions)
sla7050m unipolar stepper-motor translator/pwm driver www.allegromicro.com 11 notes: 1. exact body and lead configuration at vendor?s option within limits shown. 2. lead spacing tolerance is non-cumulative. 3. the shaded area is exposed heat spreader. 3. recommended mounting hardware torque: 0.490 - 0.822 nm. 4. recommended use of metal-oxide-filled, alkyl-degenerated oil-base silicone grease: dow corning sc102, toshiba yg6260, shin-etsu g746, or equivalent. SLA7050MLF872 dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions)
115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 sla7050m unipolar stepper-motor translator/pwm driver 12 packing information 20 sticks/tubes in y direction; 3 layers of sticks/tubes in z direction = 1080 devices per box. 18 devices per stick/tube. a rubber stopper is provided at each end of the stick/tube.

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